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Digital Isolator, Enhanced System-Level ESD Reliability ADuM3100
FEATURES
Enhanced system-level ESD performance per IEC 61000-4-x High data rate: dc to 100 Mbps (NRZ) Compatible with 3.3 V and 5.0 V operation/level translation 105C maximum operating temperature Low power operation 5 V operation 2.0 mA maximum @ 1 Mbps 5.6 mA maximum @ 25 Mbps 18 mA maximum @ 100 Mbps 3.3 V operation 1.1 mA maximum @ 1 Mbps 4.2 mA maximum @ 25 Mbps 8.3 mA maximum @ 50 Mbps 8-lead SOIC, Pb-free package High common-mode transient immunity: >25 kV/s Safety and regulatory information UL recognized: 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 VIORM = 560 VPEAK
APPLICATIONS
Digital fieldbus isolation Opto-isolator replacement Computer-peripheral interface Microprocessor system interface General instrumentation and data acquisition
FUNCTIONAL BLOCK DIAGRAM
VDD1 1 E N C O D E D E C O D E
8
VDD2
VI 2 (DATA IN)
7
GND2
VDD1 3 UPDATE GND1 4 WATCHDOG
6
VO (DATA OUT)
5
ADuM3100
GND2
05637-001
NOTES 1. FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION.
Figure 1.
GENERAL DESCRIPTION
The ADuM3100 1 is a digital isolator based on Analog Devices iCoupler(R) technology. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives, such as optocoupler devices. Configured as a pin-compatible replacement for existing high speed optocouplers, the ADuM3100 supports data rates as high as 25 Mbps and 100 Mbps. The ADuM3100 operates with a voltage supply ranging from 3.0 V to 5.5 V, boasts a propagation delay of <18 ns and an edge asymmetry of <2 ns, and is compatible with temperatures up to 105C. It operates at very low power, less than 2.0 mA of quiescent current (sum of both sides), and a dynamic current of less than 160 A per Mbps of data rate. Unlike other optocoupler alternatives, the ADuM3100 provides dc correctness with a patented refresh feature that continuously updates the output signal. The ADuM3100 is offered in two grades. The ADuM3100AR and ADuM3100BR can operate up to a maximum temperature of 105C and support data rates up to 25 Mbps and 100 Mbps, respectively. In comparison to the ADuM1100 digital isolator, the ADuM3100 contains various circuit and layout changes to provide increased capability relative to system-level IEC 610004-x testing (ESD/burst/surge). The precise capability in these tests for either the ADuM1100 or ADuM3100 is strongly determined by the design and layout of the user's board or module. For more information, see Application Note AN-793, ESD/Latch-Up Considerations with iCoupler Isolation Products.
1
Protected by U.S. Patents 5,952,849; 6,525,566; 6,922,080; 6,903,578; 6,873,065; and other pending patents.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
ADuM3100 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Electrical Specifications, 5 V Operation........................................ 3 Electrical Specifications, 3.3 V Operation..................................... 4 Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V Operation............................................................................ 5 Package Characteristics ............................................................... 7 Regulatory Information............................................................... 7 Insulation and Safety-Related Specifications............................ 7 DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics .............................................................................. 8 Recommended Operating Conditions ...................................... 8 Absolute Maximum Ratings ............................................................9 ESD Caution...................................................................................9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Applications..................................................................................... 13 PC Board Layout ........................................................................ 13 System-Level ESD Considerations and Enhancements ........ 13 Propagation Delay-Related Parameters................................... 13 Method of Operation, DC Correctness, and Magnetic Field Immunity..................................................................................... 14 Power Consumption .................................................................. 15 Outline Dimensions ....................................................................... 16 Ordering Guide .......................................................................... 16
REVISION HISTORY
3/06--Rev. 0 to Rev. A Updated Format..................................................................Universal Changes to Product Title, Features, General Description, and Note 1.......................................................................................... 1 Changes to Table 1............................................................................ 3 Changes to Table 2............................................................................ 4 Changes to Table 3............................................................................ 5 Added System-Level ESD Considerations and Enhancements Section................................................................... 13 Added Power Consumption Section............................................ 15 10/05--Revision 0: Initial Version
Rev. A | Page 2 of 16
ADuM3100 ELECTRICAL SPECIFICATIONS, 5 V OPERATION 1
4.5 V VDD1 5.5 V, 4.5 V VDD2 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDD2 = 5 V. Table 1.
Parameter DC SPECIFICATIONS Input Supply Current, Quiescent Output Supply Current, Quiescent Input Supply Current (25 Mbps) (See Figure 4) Output Supply Current 2 (25 Mbps) (See Figure 5) Input Supply Current (100 Mbps) (See Figure 4) Output Supply Current2 (100 Mbps) (See Figure 5) Input Current Logic High Output Voltage Logic Low Output Voltage Symbol IDD1 (Q) IDD2 (Q) IDD1 (25) IDD2 (25) IDD1 (100) IDD2 (100) II VOH VOL -10 VDD2 - 0.1 VDD2 - 0.8 Min Typ 1.3 0.15 3.2 0.6 10 2.1 +0.01 5.0 4.6 0.0 0.03 0.3 Max 1.8 0.25 4.5 1.1 15 2.9 +10 Unit mA mA mA mA mA mA A V V V V V Test Conditions VI = 0 V or VDD1 VI = 0 V or VDD1 12.5 MHz logic signal freq. 12.5 MHz logic signal freq. 50 MHz logic signal freq. 50 MHz logic signal freq., ADuM3100BR only 0 VIN VDD1 IO = -20 A, VI = VIH IO = -4 mA, VI = VIH IO = 20 A, VI = VIL IO = 400 A, VI = VIL IO = 4 mA, VI = VIL
0.1 0.1 0.8
SWITCHING SPECIFICATIONS For ADuM3100AR Minimum Pulse Width 3 Maximum Data Rate 4 For ADuM3100BR Minimum Pulse Width4 Maximum Data Rate4 For All Grades Propagation Delay Time to Logic Low Output 5, 6 (See Figure 6) Propagation Delay Time to Logic High Output5, 6 (See Figure 6) Pulse-Width Distortion |tPLH - tPHL|6 Change vs. Temperature 7 Propagation Delay Skew (Equal Temperature)6, 8 Propagation Delay Skew (Equal Temperature, Supplies)6, 8 Output Rise/Fall Time Common-Mode Transient Immunity at Logic Low/High Output 9 Input Dynamic Supply Current 10 Output Dynamic Supply Current10
See notes on Page 6.
PW 25
40
ns Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VI = 0 or VDD1, VCM = 1000 V
PW 100
6.7 150
10
ns Mbps
tPHL tPLH PWD
10.5 10.5 0.5 3
18 18 2
ns ns ns ps/C
tPSK1 tPSK2 tR, tF |CML|, |CMH| IDDI (D) IDDO (D) 25 3 35 0.09 0.02
8 6
ns ns ns kV/s mA/Mbps mA/Mbps
Rev. A | Page 3 of 16
ADuM3100 ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION1
3.0 V VDD1 3.6 V, 3.0 V VDD2 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDD2 = 3.3 V. Table 2.
Parameter DC SPECIFICATIONS Input Supply Current, Quiescent Output Supply Current, Quiescent Input Supply Current (25 Mbps) (See Figure 4) Output Supply Current2 (25 Mbps) (See Figure 5) Input Supply Current (50 Mbps) (See Figure 4) Output Supply Current2 (50 Mbps) (See Figure 5) Input Current Logic High Output Voltage Logic Low Output Voltage Symbol IDD1 (Q) IDD2 (Q) IDD1 (25) IDD2 (25) IDD1 (50) IDD2 (50) II VOH VOL -10 VDD2 - 0.1 VDD2 - 0.5 Min Typ 0.7 0.1 2.6 0.4 4.6 0.7 +0.01 3.3 3.0 0.0 0.04 0.3 Max 0.9 0.2 3.4 0.8 6.6 1.7 +10 Unit mA mA mA mA mA mA A V V V V V Test Conditions VI = 0 V or VDD1 VI = 0 V or VDD1 12.5 MHz logic signal freq. 12.5 MHz logic signal freq. 25 MHz logic signal freq., ADuM3100BR only 25 MHz logic signal freq., ADuM3100BR only 0 VIN VDD1 IO = -20 A, VI = VIH IO = -2.5 mA, VI = VIH IO = 20 A, VI = VIL IO = 400 A, VI = VIL IO = 2.5 mA, VI = VIL
0.1 0.1 0.4
SWITCHING SPECIFICATIONS For ADuM3100AR Minimum Pulse Width3 Maximum Data Rate4 For ADuM3100BR Minimum Pulse Width3 Maximum Data Rate4 For All Grades Propagation Delay Time to Logic Low Output5, 6 (See Figure 7) Propagation Delay Time to Logic High Output5, 6 (See Figure 7) Pulse-Width Distortion |tPLH - tPHL|6 Change vs. Temperature7 Propagation Delay Skew (Equal Temperature)6, 8 Propagation Delay Skew (Equal Temperature, Supplies)6, 8 Output Rise/Fall Time Common-Mode Transient Immunity at Logic Low/High Output9 Input Dynamic Supply Current10 Output Dynamic Supply Current10
See notes on Page 6.
PW 25 PW 50 tPHL tPLH PWD tPSK1 tPSK2 tR, tF |CML|, |CMH| IDDI (D) IDDO (D) 3 35 0.08 0.01 10 100 14.5 15.0 0.5 10
40
ns Mbps ns Mbps ns ns ns ps/C ns ns ns kV/s mA/Mbps mA/Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VI = 0 or VDD1, VCM = 1000 V, transient magnitude = 800 V
20
28 28 3 15 12
25
Rev. A | Page 4 of 16
ADuM3100 ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V OR 3 V/5 V OPERATION1
5 V/3 V operation: 4.5 V VDD1 5.5 V, 3.0 V VDD2 3.6 V. 3 V/5 V operation: 3.0 V VDD1 3.6 V, 4.5 V VDD2 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V. Table 3.
Parameter DC SPECIFICATIONS Input Supply Current, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current2, Quiescent 5 V/3 V Operation 3 V/5 V Operation Input Supply Current, 25 Mbps 5 V/3 V Operation 3 V/5 V Operation Output Supply Current2, 25 Mbps 5 V/3 V Operation 3 V/5 V Operation Input Supply Current, 50 Mbps 5 V/3 V Operation 3 V/5 V Operation Output Supply Current2, 50 Mbps 5 V/3 V Operation 3 V/5 V Operation Input Currents Logic High Output Voltage, 5 V/3 V Operation Logic Low Output Voltage, 5 V/3 V Operation Symbol IDDI (Q) 1.3 0.7 IDDO (Q) 0.1 0.15 IDDI (25) 3.2 2.6 IDDO (25) 0.4 0.6 IDDI (50) 5.5 4.6 IDDO (50) 0.7 1.1 +0.01 3.3 3.0 0.0 0.04 0.3 5.0 4.6 0.0 0.03 0.3 1.7 1.6 +10 mA mA A V V V V V V V V V V 25 MHz logic signal freq. 25 MHz logic signal freq. 0 VIA, VIB, VIC, VID VDD1 or VDD2 IO = -20 A, VI = VIH IO = -2.5 mA, VI = VIH IO = 20 A, VI = VIL IO = 400 A, VI = VIL IO = 2.5 mA, VI = VIL IO = -20 A, VI = VIH IO = -4 mA, VI = VIH IO = 20 A, VI = VIL IO = 400 A, VI = VIL IO = 4 mA, VI = VIL 8.0 6.6 mA mA 25 MHz logic signal freq. 25 MHz logic signal freq. 0.8 1.1 mA mA 12.5 MHz logic signal freq. 12.5 MHz logic signal freq. 4.5 3.4 mA mA 12.5 MHz logic signal freq. 12.5 MHz logic signal freq. 0.2 0.25 mA mA 1.8 0.9 mA mA Min Typ Max Unit Test Conditions
IIA VOH VOL
-10 VDD2 - 0.1 VDD2 - 0.5
0.1 0.1 0.4
Logic High Output Voltage, 3 V/5 V Operation Logic Low Output Voltage, 3 V/5 V Operation
VOH VOL
VDD2 - 0.1 VDD2 - 0.8
0.1 0.1 0.8
SWITCHING SPECIFICATIONS For ADuM3100AR Minimum Pulse Width3 Maximum Data Rate4 For ADuM3100BR Minimum Pulse Width3 Maximum Data Rate4 For All Grades Propagation Delay Time to Logic Low/ High Output5, 6 5 V/3 V Operation (See Figure 8) 3 V/5 V Operation (See Figure 9) Pulse-Width Distortion, |tPLH - tPHL|6 5 V/3 V Operation 3 V/5 V Operation
PW 25 PW 50 tPHL, tPLH 13 16 PWD 0.5 0.5
40
ns Mbps ns Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
20
21 26 2 3
ns ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
Rev. A | Page 5 of 16
ADuM3100
Parameter Change vs. Temperature7 5 V/3 V Operation 3 V/5 V Operation Propagation Delay Skew (Equal Temperature)6, 8 5 V/3 V Operation 3 V/5 V Operation Propagation Delay Skew (Equal Temperature, Supplies)6, 8 5 V/3 V Operation 3 V/5 V Operation Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic Low/High Output9 Input Dynamic Supply Current per Channel10 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Supply Current per Channel10 5 V/3 V Operation 3 V/5 V Operation
1 2
Symbol
Min
Typ 3 10
Max
Unit ps/C ps/C
Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
tPSK1 12 15 tPSK2 9 12 tR, tf |CML|, |CMH| IDDI (D) 0.09 0.08 IDDO (D) 0.01 0.02 mA/Mbps mA/Mbps mA/Mbps mA/Mbps 25 3 35 ns ns ns kV/s CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VI = 0 or VDD1, VCM = 1000 V, transient magnitude = 800 V ns ns
All voltages are relative to their respective ground. Output supply current values are with no output load present. See Figure 4 and Figure 5 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 3 The minimum pulse width is the shortest pulse width at which the specified pulse-width distortion is guaranteed. 4 The maximum data rate is the fastest data rate at which the specified pulse-width distortion is guaranteed. 5 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 6 Because the input thresholds of the ADuM3100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse-width distortion can be affected by slow input rise/fall times. See the System-Level ESD Considerations and Enhancements section and Figure 13 to Figure 17 for information on the impact of given input rise/fall times on these parameters. 7 Pulse-width distortion change vs. temperature is the absolute value of the change in pulse-width distortion for a 1C change in operating temperature. 8 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 9 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common-mode is slewed. 10 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 4 and Figure 5 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
Rev. A | Page 6 of 16
ADuM3100
PACKAGE CHARACTERISTICS
Table 4.
Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 Input IC Junction-to-Case Thermal Resistance Output IC Junction-to-Case Thermal Resistance Package Power Dissipation
1 2
Symbol RI-O CI-O CI JCI JCO PPD
Min
Typ 1012 1 4.0 46 41
Max
Unit pF pF C/W C/W
Test Conditions f = 1 MHz Thermocouple located at center underside of package
240
mW
Device considered a 2-terminal device: Pin 1, Pin 2, Pin 3, and Pin 4 shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 shorted together. Input capacitance is measured at Pin 2 (VI).
REGULATORY INFORMATION
The ADuM3100 is approved by the organizations listed in Table 5. Table 5.
UL Recognized under 1577 Component Recognition Program 1 File E214100
1
CSA Approved under CSA Component Acceptance Notice No. 5A, C22.2 No. 1-98, C22.2 No. 14-95, and C22.2 No. 950-95 File 205078
VDE Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 2 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 File 2471900-4880-0002
In accordance with UL 1577, each ADuM3100 is proof tested by applying an insulation test voltage 3000 V rms for 1 second (leakage detection current limit, II-O 5 A). 2 In accordance with DIN EN 60747-5-2, each ADuM3100 is proof tested by applying an insulation test voltage 1050 VPEAK for 1 second (partial discharge detection limit 5 pC). An asterisk (*) branded on the component designates DIN EN 60747-5-2 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol L(I01) L(I02) Value 4.90 min 4.01 min 0.017 min >175 IIIa Unit mm mm mm V Conditions Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1)
CTI
.
Rev. A | Page 7 of 16
ADuM3100
DIN EN 60747-5-2 (VDE 0884 PART 2) INSULATION CHARACTERISTICS
Table 7.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree (DIN VDE 0110, Table 5) Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method b1 VIORM x 1.875 = VPR, 100% Production Test, tM = 1 sec, Partial Discharge <5 pC Input-to-Output Test Voltage, Method a After Environmental Tests Subgroup 1 VIORM x 1.6 = VPR, tM = 10 sec, Partial Discharge <5 pC After Input and/or Output Safety Test Subgroup 2/3 VIORM x 1.2 = VPR, tM = 10 sec, Partial Discharge <5 pC Highest Allowable Overvoltage (Transient Overvoltage, tINI = 60 sec) Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure, See Figure 2) Case Temperature Input Current Output Current Insulation Resistance at TS, VIO = 500 V Symbol Characteristic I to IV I to III I to II 40/105/21 2 560 1050 672 896 672 4000 150 160 170 >109 Unit
VIORM VPR VPR VPR VPR VTR TS IS, INPUT IS, OUTPUT RS
VPEAK VPEAK VPEAK VPEAK VPEAK VPEAK C mA mA
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. The asterisk (*) on the package denotes DIN EN 60747-5-2 approval for 560 VPEAK working voltage.
180 160
SAFETY-LIMITING CURRENT (mA)
RECOMMENDED OPERATING CONDITIONS
Table 8.
OUTPUT CURRENT
140 120 100 80 60 40
INPUT CURRENT
Parameter Operating Temperature Supply Voltages 1 Logic High Input Voltage, 5 V Operation (See Figure 10 and Figure 11) Logic Low Input Voltage, 5 V Operation1, 2 (See Figure 10 and Figure 11) Logic High Input Voltage, 3.3 V Operation1, 2 (See Figure 10 and Figure 11) Logic Low Input Voltage, 3.3 V Operation1, 2 (See Figure 10 and Figure 11) Input Signal Rise and Fall Times
1 2
Symbol TA VDD1, VDD2 VIH
Min -40 3.0 2.0
Max +105 5.5 VDD1
Unit C V V
0 0 50 100 150 CASE TEMPERATURE (C)
200
05637-002
20
VIL
0.0
0.8
V
VIH
1.5
VDD1
V
Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Values with Case Temperature per DIN EN 60747-5-2
VIL
0.0
0.5
V
1.0
ms
All voltages are relative to their respective ground. Input switching thresholds have 300 mV of hysteresis. See the Method of Operation, DC Correctness, and Magnetic Field Immunity section, Figure 18, and Figure 19 for information on immunity to external magnetic fields.
Rev. A | Page 8 of 16
ADuM3100 ABSOLUTE MAXIMUM RATINGS
Table 9.
Parameter Storage Temperature ,TST Ambient Operating Temperature, TA Supply Voltages 1 , VDD1, VDD2 Input Voltage1, VI Output Voltage1, VO Average Current, per Pin 2 Temperature 105C Common-Mode Transients 3
1 2
Min -55 -40 -0.5 -0.5 -0.5 -25 -100
Max +150 +125 +6.5 VDD1 + 0.5 VDD2 + 0.5 +25 +100
Unit C C V V V mA kV/s
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ambient temperature = 25C, unless otherwise noted.
All voltages are relative to their respective ground. See Figure 2 for information on maximum allowable current for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the Absolute Maximum Rating can cause latchup or permanent damage.
Table 10. Truth Table (Positive Logic)
VI Input H L X X
1
VDD1 State Powered Powered Unpowered Powered
VDD2 State Powered Powered Powered Unpowered
VO Output H L H1 XX1
VO returns to VI state within 1 s of power restoration.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 9 of 16
ADuM3100 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1 1 1 VI 2 VDD1 1 3 GND1 4
1PIN 8
ADuM3100
TOP VIEW (Not to Scale)
VDD2 GND22 VO GND22
7 6 5
1 AND PIN 3 ARE INTERNALLY CONNECTED. IT IS STRONGLY RECOMMENDED THAT BOTH BE CONNECTED TO VDD1 . 2PIN 5 AND PIN 7 ARE INTERNALLY CONNECTED. IT IS STRONGLY RECOMMENDED THAT BOTH BE CONNECTED TO GND2.
Figure 3. Pin Configuration
Table 11. Pin Function Descriptions
Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 VI VDD1 GND1 GND2 VO GND2 VDD2 Description Input Supply Voltage, 3.0 V to 5.5 V Logic Input Input Supply Voltage, 3.0 V to 5.5 V Input Ground Output Ground Logic Output Output Ground Output Supply Voltage, 3.0 V to 5.5 V
Rev. A | Page 10 of 16
05637-003
ADuM3100 TYPICAL PERFORMANCE CHARACTERISTICS
20 18 16 14
18
17
PROPAGATION DELAY (ns)
CURRENT (mA)
16
12 10 8 6 4
05637-004
5V
tPHL
15
tPLH
3.3V
14
13
05637-007
2 0 0 25 50 75 100 DATA RATE (Mbps) 125
150
12 -50
-25
0
75 25 50 TEMPERATURE (C)
100
125
Figure 4. Typical Input Supply Current vs. Logic Signal Frequency for 5 V and 3.3 V Operation
5
Figure 7. Typical Propagation Delays vs. Temperature, 3.3 V Operation
14
PROPAGATION DELAY (ns)
4
13
tPLH
12
CURRENT (mA)
3 5V 2
tPHL
11
1
3.3V
05637-005
10
05637-008
0 0 25 50 75 100 DATA RATE (Mbps) 125
150
9 -50
-25
0
25 50 75 TEMPERATURE (C)
100
125
Figure 5. Typical Output Supply Current vs. Logic Signal Frequency for 5 V and 3.3 V Operation
13
Figure 8. Typical Propagation Delays vs. Temperature, 5 V/3 V Operation
18
17
PROPAGATION DELAY (ns)
PROPAGATION DELAY (ns)
12
16
tPHL
15
11
tPHL
10
tPLH
tPLH
14
13
05637-006
05637-009
9 -50
-25
0
50 75 25 TEMPERATURE (C)
100
125
12 -50
-25
0
25 50 75 TEMPERATURE (C)
100
125
Figure 6. Typical Propagation Delays vs. Temperature, 5 V Operation
Figure 9. Typical Propagation Delays vs. Temperature, 3 V/5 V Operation
Rev. A | Page 11 of 16
ADuM3100
1.7
1.4 -40C +25C
1.6
INPUT THRESHOLD, VITH (V)
1.3
-40C 1.5 +25C
INPUT THRESHOLD, VITH (V)
1.2 +125C 1.1
1.4
1.3 +125C 1.2
05637-010
1.0
0.9
05637-011
1.1 3.0 3.5 4.0 4.5 5.0 INPUT SUPPLY VOLTAGE, VDD1 (V)
5.5
0.8 3.0
3.5 4.0 4.5 5.0 INPUT SUPPLY VOLTAGE, VDD1 (V)
5.5
Figure 10. Typical Input Voltage Switching Threshold, Low-to-High Transition
Figure 11. Typical Input Voltage Switching Threshold, High-to-Low Transition
Rev. A | Page 12 of 16
ADuM3100 APPLICATIONS
PC BOARD LAYOUT
The ADuM3100 digital isolator requires no external interface circuitry for the logic interfaces. A bypass capacitor is recommended at the input and output supply pins. The input bypass capacitor can conveniently connect between Pin 3 and Pin 4 (see Figure 12). Alternatively, the bypass capacitor can be located between Pin 1 and Pin 4. The output bypass capacitor can be connected between Pin 7 and Pin 8 or Pin 5 and Pin 8. The capacitor value should be between 0.01 F and 0.1 F. The total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm.
VDD1 V1 (DATA) GND1 VDD2 (OPTIONAL) VO (DATA OUT) GND2
05637-012
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay time describes the length of time it takes for a logic signal to propagate through a component. Propagation delay time to logic low output and propagation delay time to logic high output refer to the duration between an input signal transition and the respective output signal transition (see Figure 13).
INPUT (VI) 50%
tPLH
OUTPUT (VO)
tPHL
50%
05637-013
Figure 13. Propagation Delay Parameters
Figure 12. Recommended Printed Circuit Board Layout
SYSTEM-LEVEL ESD CONSIDERATIONS AND ENHANCEMENTS
System-level ESD reliability (for example, per IEC 61000-4-x) is highly dependent on system design which varies widely by application. The ADuM3100 incorporates many enhancements to make ESD reliability less dependent on system design. The enhancements include: * ESD protection cells added to all input/output interfaces. * Key metal trace resistances reduced using wider geometry and paralleling of lines with vias. * The SCR effect inherent in CMOS devices minimized by use of guarding and isolation technique between PMOS and NMOS devices. * Areas of high electric field concentration eliminated using 45 corners on metal traces. * Supply pin overvoltage prevented with larger ESD clamps between each supply pin and its respective ground. While the ADuM3100 improves system-level ESD reliability, it is no substitute for a robust system-level design. See Application Note AN-793, ESD/Latch-Up Considerations with iCoupler Isolation Products for detailed recommendations on board layout and system-level design.
Pulse-width distortion is the maximum difference between tPLH and tPHL and provides an indication of how accurately the input signal timing is preserved in the component output signal. Propagation delay skew is the difference between the minimum and maximum propagation delay values among multiple ADuM3100 components operated at the same operating temperature and having the same output load. Depending on the input signal rise/fall time, the measured propagation delay based on the input 50% level can vary from the true propagation delay of the component (as measured from its input switching threshold). This is due to the fact that the input threshold, as is the case with commonly used optocouplers, is at a different voltage level than the 50% point of typical input signals. This propagation delay difference is: LH = tPLH - tPLH = (tr/0.8 VI)(0.5 V1 - VITH (L-H)) HL = tPHL - tPHL = (tf/0.8 VI)(0.5 V1 - VITH (H-L)) where: tPLH, tPHL = propagation delays as measured from the input 50%. tPLH, tPHL = propagation delays as measured from the input switching thresholds. tr, tf = input 10% to 90% rise/fall time. VI = amplitude of input signal (0 to VI levels assumed). VITH (L-H), VITH (H-L) = input switching thresholds.
VI VITH(L-H) INPUT (VI)
LH 50%
HL
VITH(H-L)
tPLH t'PLH
OUTPUT (VO) 50%
tPHL
t'PHL
05637-014
Figure 14. Impact of Input Rise/Fall Time on Propagation Delay
Rev. A | Page 13 of 16
ADuM3100
4
PROPAGATION DELAY CHANGE, LH (ns) PULSE-WIDTH DISTORTION ADJUSTMENT, PWD (ns)
6
5
3
4 5V INPUT SIGNAL 3 3.3V INPUT SIGNAL 2
5V INPUT SIGNAL 2
1
05637-015
0 1 2 3 4 8 5 6 7 INPUT RISE TIME (10%-90%, ns) 9
0 1 2 3 4 5 6 7 8 INPUT RISE/FALL TIME (10%-90%, ns) 9
10
10
Figure 15. Typical Propagation Delay Change due to Input Rise Time Variation (for VDD1 = 3.3 V and 5 V)
0
PROPAGATION DELAY CHANGE, HL (ns)
Figure 17. Typical Pulse-Width Distortion Adjustment due to Input Rise/Fall Time Variation (at VDD1 = 3.3 V and 5 V)
METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY
5V INPUT SIGNAL
-1
-2 3.3V INPUT SIGNAL
-3
05637-016
-4 1 2 3 5 6 7 4 8 INPUT RISE TIME (10%-90%, ns) 9
10
Figure 16. Typical Propagation Delay Change due to Input Fall Time Variation (for VDD1 = 3.3 V and 5 V)
Referring to Figure 1, the two coils act as a pulse transformer. Positive and negative logic transitions at the isolator input cause narrow (2 ns) pulses to be sent via the transformer to the decoder. The decoder is bistable and therefore either set or reset by the pulses indicating input logic transitions. In the absence of logic transitions at the input for more than 2 s, a periodic update pulse of the appropriate polarity is sent to ensure dc correctness at the output. If the decoder does not receive any of these update pulses for more than approximately 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a logic high state by the watchdog timer circuit. The limitation on the ADuM3100 magnetic field immunity is set by the condition in which induced voltage in the transformer receiving coil is sufficiently large to either falsely set or reset the decoder. The analysis that follows defines the conditions under which this can occur. The ADuM3100 3.3 V operating condition is examined because it represents the most susceptible mode of operation. The pulses at the transformer output are greater than 1.0 V in amplitude. The decoder has sensing thresholds at about 0.5 V, therefore establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt) rn2, n = 1, 2, . . . , N where: = magnetic flux density (gauss). N = number of turns in receiving coil. rn = radius of nth turn in receiving coil (cm).
The impact of the slower input edge rates can also affect the measured pulse-width distortion as based on the input 50% level. This impact can either increase or decrease the apparent pulse-width distortion depending on the relative magnitudes of tPHL, tPLH, and PWD. The case of interest here is the condition that leads to the largest increase in pulse-width distortion. The change in this case is given by PWD = PWD - PWD = LH - HL = (t/0.8 V1)(V - VITH (L-H) - VITH (H-L)),(for t = tr = tf) where: PWD = |tPLH - tPHL| PWD = |tPLH - tPHL| This adjustment in pulse-width distortion is plotted as a function of input rise/fall time in Figure 17.
Rev. A | Page 14 of 16
05637-017
3.3V INPUT SIGNAL
1
ADuM3100
MAXIMUM ALLOWABLE CURRENT (kA)
Given the geometry of the receiving coil in the ADuM3100 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 18.
100
1000 DISTANCE = 1m 100
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
05637-019
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
10
1
0.1
0.01 1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
0.01
05637-018
Figure 19. Maximum Allowable Current for Current-to-ADuM3100 Spacings
0.001 1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 18. Maximum Allowable External Magnetic Field
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V--still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM3100 transformers. Figure 19 shows the allowable current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM3100 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted, one would have to place a current of 0.5 kA 5 mm away from the ADuM3100 to affect the component's operation.
POWER CONSUMPTION
The supply current of the ADuM3100 isolator is a function of the supply voltage, the input data rate, and the output load. The input supply current is given by IDDI = IDDI (Q) IDDI = IDDI (D) x (2f - fr) + IDDI (Q) The output supply current is given by IDDO = IDDO (Q)
-3
f 0.5fr f > 0.5fr
f 0.5fr
IDDO = (IDDO (D) + (0.5 x 10 ) x CLVDDO) x (2f - fr) + IDDO (Q) f > 0.5fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
Rev. A | Page 15 of 16
ADuM3100 OUTLINE DIMENSIONS
5.00 (0.1968) 4.80 (0.1890)
8 5
4.00 (0.1574) 3.80 (0.1497) 1
6.20 (0.2440)
4 5.80 (0.2284)
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040)
1.75 (0.0688) 1.35 (0.0532)
0.50 (0.0196) x 45 0.25 (0.0099)
0.51 (0.0201) COPLANARITY SEATING 0.31 (0.0122) 0.10 PLANE
8 0.25 (0.0098) 0 1.27 (0.0500) 0.40 (0.0157) 0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 20. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADuM3100ARZ 1 ADuM3100ARZ-RL71 ADUM3100BRZ1 ADUM3100BRZ-RL71
1
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Max Data Rate (Mbps) 25 25 100 100
Minimum Pulse Width (ns) 40 40 10 10
Package Description 8-Lead SOIC_N 8-Lead SOIC_N, 1,000 Piece Reel 8-Lead SOIC_N 8-Lead SOIC_N, 1,000 Piece Reel
Package Option R-8 R-8 R-8 R-8
Z = Pb-free part.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05637-0-3/06(A)
Rev. A | Page 16 of 16

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